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商品编号:
74LVT125PW,118
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简述:
3.3 V quad buffer; 3-state
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描述:
The 74LVT125; 74LVTH125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
- 数据手册:
特性
Quad bus interface
3-state buffers
Wide supply voltage range from 2.7 to 3.6 V
BiCMOS high speed and output drive
Output capability: +64 mA and -32 mA
Direct interface with TTL levels
Overvoltage tolerant inputs to 5.5 V
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up 3-state
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V
Specified from -40 °C to 85 °C
