在线客服
我的收藏
|免费注册
English
Default welcome nexperia!
产品搜索
    购物车
    共 2557件相关商品
    产品
    描述
    价格
    库存
    DC
    数据手册
    操作
    HEF4094B
    HEF4094BT,653
    8-stage shift-and-store register

    • Fully static operation

    • 5 V, 10 V, and 15 V parametric ratings

    • Wide supply voltage range from 3.0 to 15.0 V

    • CMOS low power dissipation

    • High noise immunity

    • Standardized symmetrical output characteristics

    • ESD protection:

      • HBM JESD22-A114F exceeds 2000 V

      • MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)

    • Complies with JEDEC standard JESD 13-B

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥0.8224

    500+:¥0.7476

    1000+:¥0.7120

    3000+:¥0.6781

    450,000
    2520+
    数据手册
    74HC4052
    74HC4052D,653
    Dual 4-channel analog multiplexer/demultiplexer

    • Wide analog input voltage range from -5 V to +5 V

    • CMOS low power dissipation
    • High noise immunity
    • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

    • Low ON resistance:

      • 80 Ω (typical) at VCC - VEE = 4.5 V

      • 70 Ω (typical) at VCC - VEE = 6.0 V

      • 60 Ω (typical) at VCC - VEE = 9.0 V

    • Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals

    • Typical ‘break before make’ built-in

    • Complies with JEDEC standards:
      • JESD8C (2.7 V to 3.6 V)
      • JESD7A (2.0 V to 6.0 V)

    • Input levels:

      • For 74HC4052: CMOS level

      • For 74HCT4052: TTL level

    • ESD protection:

      • HBM JESD22-A114F exceeds 2000 V

      • MM JESD22-A115-A exceeds 200 V

      • CDM JESD22-C101E exceeds 1000 V

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥0.8041

    500+:¥0.7310

    1000+:¥0.6962

    3000+:¥0.6630

    350,000
    2526+
    数据手册
    74LVC8T245
    74LVC8T245PW,118
    8-bit dual supply translating transceiver; 3-state

    • Wide supply voltage range:

      • VCC(A): 1.2 V to 5.5 V

      • VCC(B): 1.2 V to 5.5 V

    • High noise immunity

    • Complies with JEDEC standards:

      • JESD8-7 (1.2 V to 1.95 V)

      • JESD8-5 (1.8 V to 2.7 V)

      • JESD8C (2.7 V to 3.6 V)

      • JESD36 (4.5 V to 5.5 V)

    • Maximum data rates:

      • 420 Mbps (3.3 V to 5.0 V translation)

      • 210 Mbps (translate to 3.3 V)

      • 140 Mbps (translate to 2.5 V)

      • 75 Mbps (translate to 1.8 V)

      • 60 Mbps (translate to 1.5 V)

    • Suspend mode

    • Latch-up performance exceeds 100 mA per JESD 78B Class II

    • ±24 mA output drive (VCC = 3.0 V)

    • Inputs accept voltages up to 5.5 V

    • Low power consumption: 30 μA maximum ICC

    • IOFF circuitry provides partial Power-down mode operation

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 4000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥2.9775

    500+:¥2.7069

    1000+:¥2.5780

    3000+:¥2.4552

    300,000
    2529+
    数据手册
    HEF4093B
    HEF4093BT,653
    Quad 2-input NAND Schmitt trigger

    • Schmitt trigger input discrimination

    • Fully static operation

    • 5 V, 10 V, and 15 V parametric ratings

    • Wide supply voltage range from 3.0 V to 15.0 V

    • CMOS low power dissipation

    • High noise immunity

    • Standardized symmetrical output characteristics

    • Complies with JEDEC standard JESD 13-B

    • ESD protection:

      • HBM JESD22-A114F exceeds 2000 V

      • MM JESD22-A115-B exceeds 200 V

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥0.7694

    500+:¥0.6994

    1000+:¥0.6661

    3000+:¥0.6344

    257,500
    2530+
    数据手册

    限量供应

    74HC4051
    74HC4051PW,118
    8-channel analog multiplexer/demultiplexer

    • Wide analog input voltage range from -5 V to +5 V

    • CMOS low power dissipation

    • High noise immunity

    • Complies with JEDEC standards

      • JESD8C (2.7 V to 3.6 V)
      • JESD7A (2.0 V to 6.0 V)
    • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

    • Low ON resistance:

      • 80 Ω (typical) at VCC - VEE = 4.5 V

      • 70 Ω (typical) at VCC - VEE = 6.0 V

      • 60 Ω (typical) at VCC - VEE = 9.0 V

    • Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals

    • Typical ‘break before make’ built-in

    • ESD protection:

      • HBM: ANSI/ESDA/Jedec JS-001 Class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1000 V

    • Multiple package options

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥0.7756

    484+:¥0.4446

    500+:¥0.7050

    1000+:¥0.6715

    3000+:¥0.6395

    160,484
    2347+
    数据手册
    74HC164
    74HC164PW,118
    8-bit serial-in, parallel-out shift register

    • Wide supply voltage range from 2.0 to 6.0 V

    • CMOS low power dissipation

    • High noise immunity

    • Input levels:

      • For 74HC164: CMOS level

      • For 74HCT164: TTL level

    • Gated serial data inputs

    • Asynchronous master reset

    • Complies with JEDEC standards

      • JESD8C (2.7 V to 3.6 V)

      • JESD7A (2.0 V to 6.0 V)

    • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

    • ESD protection:

      • HBM JESD22-A114F exceeds 2000 V

      • MM JESD22-A115-A exceeds 200 V

    • Multiple package options

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C.

    1+:¥0.6653

    500+:¥0.6048

    1000+:¥0.5760

    3000+:¥0.5486

    150,000
    2530+
    数据手册
    74HC125
    74HC125D,653
    Quad buffer/line driver; 3-state

    • Wide supply voltage range from 2.0 to 6.0 V

    • CMOS low power dissipation

    • High noise immunity

    • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

    • Complies with JEDEC standards:

      • JESD8C (2.7 V to 3.6 V)

      • JESD7A (2.0 V to 6.0 V)

    • Input levels:

      • The 74HC125: CMOS levels

      • The 74HCT125: TTL levels

    • ESD protection:

      • HBM JESD22-A114F exceeds 2000 V

      • MM JESD22-A115-A exceeds 200 V

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

    1+:¥0.6032

    500+:¥0.5484

    1000+:¥0.5223

    3000+:¥0.4636

    107,480
    2514+
    数据手册

    限量供应

    74AHC1G79
    74AHCT1G79GW,125
    Single D-type flip-flop; positive-edge trigger

    • Wide supply voltage range from 2.0 to 5.5 V

    • Overvoltage tolerant inputs to 5.5 V

    • High noise immunity

    • CMOS low power dissipation

    • Latch-up performance exceeds 100 mA per JESD 78 Class II Level A

    • Symmetrical output impedance

    • Balanced propagation delays

    • Input levels:

      • For 74AHC1G79: CMOS level

      • For 74AHCT1G79: TTL level

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    • Specified from -40 °C to +125 °C

    1+:¥0.3479

    500+:¥0.3163

    1000+:¥0.3012

    3000+:¥0.2869

    99,000
    2322+
    数据手册
    74LVC4245A
    74LVC4245APW,118
    Octal dual supply translating transceiver; 3-state

    • 5 V tolerant inputs/outputs, for interfacing with 5 V logic

    • Wide supply voltage range:

      • 3 V bus (VCC(B)): 1.5 V to 3.6 V

      • 5 V bus (VCC(A)): 1.5 V to 5.5 V

    • CMOS low-power consumption

    • TTL interface capability at 3.3 V

    • Overvoltage tolerant control inputs to 5.5 V

    • High-impedance when VCC(A) = 0 V

    • Complies with JEDEC standard no. JESD8B/JESD36

    • Latch-up performance meets requirements of JESD78 Class 1

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    • Multiple package options

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥1.9439

    500+:¥1.7672

    1000+:¥1.6830

    3000+:¥1.6029

    54,930
    2518+
    数据手册
    HEF4050B
    HEF4050BT,653
    Hex non-inverting buffers

    • Accepts input voltages in excess of the supply voltage

    • Fully static operation

    • 5 V, 10 V, and 15 V parametric ratings

    • Standardized symmetrical output characteristics

    • Specified from -40 °C to +85 °C

    • Complies with JEDEC standard JESD 13-B

    1+:¥1.0163

    500+:¥0.9239

    1000+:¥0.8799

    3000+:¥0.8380

    42,500
    2434+
    数据手册
    74LVC14A
    74LVC14APW,118
    Hex inverting Schmitt trigger with 5 V tolerant input

    • Wide supply voltage range from 1.2 V to 3.6 V

    • Overvoltage tolerant inputs to 5.5 V

    • CMOS low-power consumption

    • Direct interface with TTL levels

    • Unlimited input rise and fall times

    • Complies with JEDEC standard JESD8-C/JESD36 (2.7 V to 3.6 V)

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    • Multiple package options

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

    1+:¥0.5408

    500+:¥0.4916

    1000+:¥0.4682

    3000+:¥0.4459

    35,000
    2517+
    数据手册
    74LV165A
    74LV165APW,118
    8-bit parallel-in/serial-out shift register

    • Wide supply voltage range from 2.0 V to 5.5 V

    • Synchronous parallel-to-serial applications

    • Synchronous serial input for easy expansion

    • Latch-up performance exceeds 250 mA

    • CMOS LOW power consumption

    • 5.5 V tolerant inputs/outputs

    • Direct interface with TTL levels (2.7 V to 3.6 V)

    • Power-down mode

    • Complies with JEDEC standards:

      • JESD8-5 (2.3 V to 2.7 V)

      • JESD8B/JESD36 (2.7 V to 3.6 V)

      • JESD8-1A (4.5 V to 5.5 V)

    • ESD protection:

      • HBM JESD22-A114-A exceeds 2000 V

      • MM JESD22-A115-A exceeds 200 V

    • Specified from -40 °C to +85 °C

    1+:¥0.9643

    500+:¥0.8766

    1000+:¥0.8349

    3000+:¥0.7951

    27,500
    2525+
    数据手册
    74LVC2G00
    74LVC2G00DC,125
    Dual 2-input NAND gate

    • Wide supply voltage range from 1.65 V to 5.5 V

    • 5 V tolerant outputs for interfacing with 5 V logic

    • High noise immunity

    • ±24 mA output drive (VCC = 3.0 V)

    • CMOS low power dissipation

    • IOFF circuitry provides partial Power-down mode operation

    • Complies with JEDEC standard:

      • JESD8-7 (1.65 V to 1.95 V)

      • JESD8-5 (2.3 V to 2.7 V)

      • JESD8-B/JESD36 (2.7 V to 3.6 V)

    • Latch-up performance exceeds 250 mA

    • Direct interface with TTL levels

    • Overvoltage tolerant inputs to 5.5 V

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    • Multiple package options

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥1.1786

    500+:¥1.0714

    1000+:¥1.0204

    3000+:¥0.9718

    18,000
    2424+
    数据手册

    限量供应

    74LVC2G86
    74LVC2G86GT,115
    Dual 2-input EXCLUSIVE-OR gate

    • Wide supply voltage range from 1.65 V to 5.5 V

    • Overvoltage tolerant inputs to 5.5 V

    • High noise immunity

    • CMOS low-power dissipation

    • ±24 mA output drive (VCC = 3.0 V)

    • Latch-up performance exceeds 250 mA

    • Direct interface with TTL levels

    • IOFF circuitry provides partial Power-down mode operation

    • Complies with JEDEC standard:

      • JESD8-7 (1.65 V to 1.95 V)

      • JESD8-5 (2.3 V to 2.7 V)

      • JESD8C (2.7 V to 3.6 V)

      • JESD36 (4.5 V to 5.5 V)

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    • Multiple package options

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥0.6244

    500+:¥0.5677

    1000+:¥0.5406

    3000+:¥0.5149

    5000+:¥0.4555

    15000+:¥0.4555

    15,000
    2352+
    数据手册
    74HC2G34
    74HCT2G34GV,125
    Dual buffer gate

    • Wide supply voltage range from 2.0 V to 6.0 V

    • High noise immunity

    • CMOS low power dissipation

    • Balanced propagation delays

    • Unlimited input rise and fall times

    • Input levels:

      • For 74HC2G34: CMOS level

      • For 74HCT2G34: TTL level

    • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

    • Complies with JEDEC standards

      • JESD8C (2.7 V to 3.6 V)

      • JESD7A (2.0 V to 6.0 V)

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥0.6236

    500+:¥0.5669

    1000+:¥0.5399

    3000+:¥0.5142

    15,000
    数据手册
    74AUP1G57
    74AUP1G57GM,115
    Low-power configurable multiple function gate

    • Wide supply voltage range from 0.8 V to 3.6 V

    • CMOS low power dissipation

    • High noise immunity

    • Overvoltage tolerant inputs to 3.6 V

    • Low noise overshoot and undershoot < 10 % of VCC

    • IOFF circuitry provides partial power-down mode operation

    • Latch-up performance exceeds 100 mA per JESD 78 Class II

    • Low static power consumption; ICC = 0.9 μA (maximum)

    • Complies with JEDEC standards:

      • JESD8-12 (0.8 V to 1.3 V)

      • JESD8-11 (0.9 V to 1.65 V)

      • JESD8-7 (1.65 V to 1.95 V)

      • JESD8-5 (2.3 V to 2.7 V)

      • JESD8C (2.7 V to 3.6 V)

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    • Multiple package options

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥0.6022

    500+:¥0.5475

    1000+:¥0.5214

    3000+:¥0.4476

    15,000
    2522+
    数据手册

    限量供应

    74HC4094
    74HC4094PW,118
    8-stage shift-and-store bus register

    • Complies with JEDEC standard JESD7A

    • Input levels:

      • For 74HC4094: CMOS level

      • For 74HCT4094: TTL level

    • Low-power dissipation

    • ESD protection:

      • HBM JESD22-A114F exceeds 2 kV

      • MM JESD22-A115-A exceeds 200 V

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

    1+:¥0.9531

    500+:¥0.8665

    1000+:¥0.8252

    2500+:¥0.4667

    3000+:¥0.7859

    12500+:¥0.4667

    12,500
    2342+
    数据手册

    限量供应

    74LVC1G17
    74LVC1G17GV,125
    Single Schmitt trigger buffer

    • Wide supply voltage range from 1.65 V to 5.5 V

    • Overvoltage tolerant inputs to 5.5 V

    • High noise immunity

    • CMOS low power dissipation

    • IOFF circuitry provides partial Power-down mode operation

    • ±24 mA output drive (VCC = 3.0 V)

    • Latch-up performance exceeds 250 mA

    • Direct interface with TTL levels

    • Unlimited rise and fall times

    • Complies with JEDEC standard:

      • JESD8-7 (1.65 V to 1.95 V)

      • JESD8-5 (2.3 V to 2.7 V)

      • JESD8C (2.7 V to 3.6 V)

      • JESD36 (4.5 V to 5.5 V)

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    • Multiple package options

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥0.2552

    500+:¥0.2320

    1000+:¥0.2209

    3000+:¥0.2104

    11,980
    2347+
    数据手册

    限量供应

    74LVT245
    74LVT245D,118
    3.3 V octal transceiver with direction pin; 3-state

    • Wide supply voltage range from 2.7 to 3.6 V

    • 3-state buffers

    • Octal bidirectional bus interface

    • Overvoltage tolerant inputs to 5.5 V

    • Direct interface with TTL levels

    • BiCMOS high speed and output drive

    • Output capability: +64 mA/-32 mA

    • Latch-up protection exceeds 500 mA per JESD78 class II level A

    • Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs

    • No bus current loading when output is tied to 5 V bus

    • Live insertion/extraction permitted

    • Power-up 3-state

    • IOFF circuitry provides partial Power-down mode operation

    • Complies with JEDEC standards JESD8C (2.7 V to 3.6 V)

    • ESD protection:

      • HBM JESD22-A114E exceeds 2000 V

      • MM JESD22-A115-A exceeds 200 V

    • Specified from -40 °C to 85 °C

    1+:¥2.1296

    500+:¥1.9360

    1000+:¥1.8438

    2000+:¥0.7694

    3000+:¥1.7560

    10000+:¥0.7694

    10,000
    2348+
    数据手册

    限量供应

    74LVC2G38
    74LVC2G38GXX
    Dual 2-input NAND gate; open drain

    • Wide supply voltage range from 1.65 V to 5.5 V

    • 5 V tolerant outputs for interfacing with 5 V logic

    • Overvoltage tolerant inputs to 5.5 V

    • High noise immunity

    • CMOS low power dissipation

    • IOFF circuitry provides partial Power-down mode operation

    • ±24 mA output drive (VCC = 3.0 V)

    • Open-drain outputs

    • Latch-up performance exceeds 250 mA

    • Direct interface with TTL levels

    • Complies with JEDEC standard:

      • JESD8-7 (1.65 V to 1.95 V)

      • JESD8-5 (2.3 V to 2.7 V)

      • JESD8C (2.7 V to 3.6 V)

      • JESD36 (4.5 V to 5.5 V)

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    • Multiple package options

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    1+:¥1.3734

    500+:¥1.2486

    1000+:¥1.1891

    3000+:¥1.1325

    10000+:¥0.4715

    10,000
    2325+
    数据手册