High current

Three current gain selections

High switching speed: t_rr ≤ 4 ns

Low capacitance

Low leakage current

Reverse voltage: V_R ≤ 100 V

Repetitive peak reverse voltage: V_RRM ≤ 100 V

Bidirectional ESD protection of one line

Extremely low diode capacitance C_d = 0.25 pF

Minimized capacitance variation over voltage

ESD protection up to ±10 kV according to IEC 61000-4-2

Ultra small SMD package

Forward current: I_F ≤ 0.5 A

Reverse voltage: V_R ≤ 30 V

Very low forward voltage

Ultra small SMD plastic package

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Wide supply voltage range from 3.0 to 15.0 V

CMOS low power dissipation

High noise immunity

Standardized symmetrical output characteristics

ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)

Complies with JEDEC standard JESD 13-B

Specified from -40 °C to +85 °C and -40 °C to +125 °C

Reverse stand-off voltage: V_RWM = 24 V

Low clamping voltage: V_CL= 33 V at I_PP = 3.5 A

Typ. diode capacitance matching: ∆C_d/C_d = 0.1 %

ESD protection up to 30 kV (IEC 61000-4-2)

ESD protection up to 30 kV (ISO 10605; C = 330 pF, R = 330 Ω)

ISO 7637-3: Pulse a: V_S = -150 V / Pulse b: V_S = +100 V

Ultra low leakage current: I_RM < 1 nA

Qualified according to AEC-Q101 / Automotive grade

Bidirectional ESD protection of one line

Femtofarad capacitance: C_d = 400 fF

Low ESD clamping voltage: 30 V at 30 ns and ± 8 kV

Very low leakage current: I_RM < 1 nA

ESD protection up to 10 kV

IEC 61000-4-2; level 4 (ESD)

Qualified according to AEC-Q101 and recommended for use in automotive applications

Bidirectional ESD protection of one line

Extremely low diode capacitance C_d = 0.2 pF

ESD protection up to ±20 kV according to IEC 61000-4-2

Ultra small SMD package

Wide analog input voltage range from -5 V to +5 V

Low ON resistance:

• 80 Ω (typical) at V_CC - V_EE = 4.5 V

• 70 Ω (typical) at V_CC - V_EE = 6.0 V

• 60 Ω (typical) at V_CC - V_EE = 9.0 V

Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals

Typical ‘break before make’ built-in

Input levels:

• For 74HC4052: CMOS level

• For 74HCT4052: TTL level

ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• CDM JESD22-C101E exceeds 1000 V

Specified from -40 °C to +85 °C and -40 °C to +125 °C

Wide supply voltage range:

• V_CC(A): 1.2 V to 5.5 V

• V_CC(B): 1.2 V to 5.5 V

High noise immunity

Complies with JEDEC standards:

• JESD8-7 (1.2 V to 1.95 V)

• JESD8-5 (1.8 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• JESD36 (4.5 V to 5.5 V)

Maximum data rates:

• 420 Mbps (3.3 V to 5.0 V translation)

• 210 Mbps (translate to 3.3 V)

• 140 Mbps (translate to 2.5 V)

• 75 Mbps (translate to 1.8 V)

• 60 Mbps (translate to 1.5 V)

Suspend mode

Latch-up performance exceeds 100 mA per JESD 78B Class II

±24 mA output drive (V_CC = 3.0 V)

Inputs accept voltages up to 5.5 V

Low power consumption: 30 μA maximum I_CC

I_OFF circuitry provides partial Power-down mode operation

ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 4000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

Specified from -40 °C to +85 °C and -40 °C to +125 °C

Schmitt trigger input discrimination

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Wide supply voltage range from 3.0 V to 15.0 V

CMOS low power dissipation

High noise immunity

Standardized symmetrical output characteristics

Complies with JEDEC standard JESD 13-B

ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-B exceeds 200 V

Specified from -40 °C to +85 °C and -40 °C to +125 °C

Rated peak pulse power: P_PPM = 400 W

Reverse standoff voltage range: V_RWM = 24 V

Reverse current: I_RM = 0.001 μA

Small plastic package suitable for surface-mounted design

Very low package height: 1 mm

AEC-Q101 qualified

Bidirectional ESD protection of one line

Very low diode capacitance: C_d = 11 pF

Max. peak pulse power: P_PPM = 45 W

Low clamping voltage: V_CL = 12.5 V

Ultra low leakage current: I_RM < 1 nA

ESD protection up to 30 kV

IEC 61000-4-2; level 4 (ESD)

IEC 61000-4-5 (surge); I_PPM = 4.8 A

High thermal power dissipation capability

Suitable for high temperature applications up to 175 °C

Reduced Printed-Circuit Board (PCB) requirements comparing to transistors in DPAK

High energy efficiency due to less heat generation

AEC-Q101 qualified

Wide analog input voltage range from -5 V to +5 V

CMOS low power dissipation

High noise immunity

Complies with JEDEC standards

• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)

Low ON resistance:

• 80 Ω (typical) at V_CC - V_EE = 4.5 V

• 70 Ω (typical) at V_CC - V_EE = 6.0 V

• 60 Ω (typical) at V_CC - V_EE = 9.0 V

Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals

Typical ‘break before make’ built-in

ESD protection:

• HBM: ANSI/ESDA/Jedec JS-001 Class 2 exceeds 2000 V

• CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1000 V

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

High current (max. 500 mA)

Low voltage (max. 80 V)

Wide supply voltage range from 2.0 to 6.0 V

CMOS low power dissipation

High noise immunity

Input levels:

• For 74HC164: CMOS level

• For 74HCT164: TTL level

Gated serial data inputs

Asynchronous master reset

Complies with JEDEC standards

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C.

100 mA output current capability

Built-in bias resistors

Simplifies circuit design

Reduces component count

Reduces pick and place costs

AEC-Q101 qualified