图像仅供参考
请参阅产品规格
-
商品编号:
74LV595PW,118
-
批次:
2528+
-
简述:
8-bit serial-in/serial-out or parallel-out shift register; 3-state
-
描述:
The 74LV595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.
- 数据手册:
特性
Wide supply voltage range from 1.0 V to 3.6 V
CMOS low power dissipation
Direct interface with TTL levels
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C
Has a shift register with direct clear
Output capability:
Parallel outputs; bus driver
Serial output; standard
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to 85 °C and -40 °C to 125 °C
目标应用
Serial-to-parallel data conversion
Remote control holding register
