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商品编号:
74HC237D-Q100J
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简述:
Q100 - 3-to-8 line decoder, demultiplexer with address latches
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描述:
The 74HC237-Q100 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237-Q100 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237-Q100 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237-Q100 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
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特性
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Combines 3-to-8 decoder with 3-bit latch
Multiple input enable for easy expansion or independent controls
Active HIGH mutually exclusive outputs
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2 kV
HBM JESD22-A114F exceeds 2 kV
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
