The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OE_AB and OE _BA) latch enable (LE_AB and LE_BA)and clock (CP _AB and CP _BA) inputs. For A-to-B data flow, the device operates in the transparent mode when LE_AB is High. When LE_AB is Low, the A data is latched if CP _AB is held at a High or Low logic level. If LE_AB is Low, the A-bus data is stored in the latch/flip-flop on the High-to-Low transition of CP _AB. When OE_AB is High, the outputs are active. When OE_AB is Low, the outputs are in the high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OE _BA LE_BA and CP _BA. The output enables are complimentary (OE_AB is active High, and OE _BA is active Low).

To ensure the high impedance state during power up or power down, OE _BA should be tied to V_CC through a pullup resistor and OE_AB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.