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请参阅产品规格
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商品编号:
74HCS166BQX
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简述:
8-bit parallel-in/serial out shift register with Schmitt-trigger
inputs -
描述:
The 74HCS166 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial
data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel
enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next
LOW-to-HIGH transition of the clock input (CP). When PE is HIGH, data enters the register serially
at DS with each LOW-to-HIGH transition of CP. When the clock enable input (CE) is LOW data is
shifted on the LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
All inputs are Schmitt-trigger inputs, capable of transforming slowly changing input signals into
sharply defined, jitter-free output signals. - 数据手册:
特性
• Wide supply voltage range from 2.0 V to 6.0 V
• Schmitt-trigger inputs
• Low power consumption
• Typical supply current (ICC) of 100 nA
• Typical input leakage current (II) of ±10 nA
• ±7.8 mA output drive at 6 V
• 8-bit serial input and 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
• JESD7A (2.0 V to 6.0 V)
• ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 class 3A exceeds 4000 V
• CDM ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1500 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C