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商品编号:
74LV165PW-Q100J
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简述:
Q100 - 8-bit parallel-in/serial-out shift register
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描述:
The 74LV165-Q100 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
- 数据手册:
特性
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.0 to 5.5 V
CMOS low power dissipation
Direct interface with TTL levels (2.7 V to 3.6 V)
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Optimized for low voltage applications: 1.0 V to 3.6 V
Synchronous parallel-to-serial applications
Synchronous serial input for easy expansion
Complies with JEDEC standards:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- JESD36 (4.5 V to 5.5 V)
ESD protection:
MIL-STD-833, method 3015 exceeds 2 kV
HBM JESD22-A114F exceeds 2 kV
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
