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商品编号:
74HCS16507D-Q100J
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简述:
8-bit parallel-load shift register with Schmitt-trigger inputs
and open-drain outputs -
描述:
The 74HCS16507-Q100 is an 8-bit serial or parallel-in/serial-out shift register with open-drain
outputs. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two
complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data
from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the
register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-
HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
All inputs are Schmitt-trigger inputs, capable of transforming slowly changing input signals into
sharply defined, jitter-free output signals.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications. - 数据手册:
特性
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 2.0 V to 6.0 V
• Schmitt-trigger inputs
• Low power consumption
• Typical supply current (ICC) of 100 nA
• Typical input leakage current (II) of ±10 nA
• ±7.8 mA output drive at 6 V
• 8-bit serial input and 8-bit serial or parallel output
• Shift register with open-drain outputs
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
• JESD7A (2.0 V to 6.0 V)
• ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 class 3A exceeds 4000 V
• CDM ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1500 V
• Multiple package option
目标应用
• Parallel-to-serial data conversion
• Remote control holding register
• Output expansion
• LED matrix control
• 7-segment display control
• 8-bit data storage