图像仅供参考
请参阅产品规格
-
商品编号:
74ALVCH162601DGG:1
-
简述:
18-bit universal bus transceiver with 30 Ohm termination resistor; 3-state
-
描述:
The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OE AB and OE BA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OE AB is LOW, the outputs are active. When OE AB is HIGH, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CE BA/CE AB).
Data flow for B-to-A is similar to that of A-to-B but uses OE BA,LEBA and CPBA.
To ensure the high-impedance state during power-down, OE BA and OE AB should be tied to VCC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
The 74ALVCH162601 is designed with 30 Ω series resistors in both HIGH or LOW output stage.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
- 数据手册:
特性
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE™™ flow-through standard pin-out architecture
Low inductance multiple VCC and ground pins for minimum noise and ground bounce
All data inputs have bus hold circuitry
Integrated 30 Ω termination resistors
