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商品编号:
74AHC573PW,118
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简述:
type transparent latch; 3-state
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描述:
The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
- 数据手册:
特性
Wide supply voltage range from 2.0 V to 5.5 V
Balanced propagation delays
All inputs have Schmitt-trigger action
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
Common 3-state output enable input
Functionally identical to the 74AHC373; 74AHCT373
Input levels:
For 74AHC573: CMOS input level
For 74AHCT573: TTL input level
- ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
