74LVC2G00GXX

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74LVC2G00

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商品编号:
74LVC2G00GXX
简述:
Dual 2-input NAND gate
描述:
The 74LVC2G00 is a dual 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
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库存：10,000

价格（包含13%的增值税）

数量单价总价: 1¥1.3734¥1.3734; 500¥1.2486¥624.3000; 1000¥1.1891¥1,189.1000; 3000¥1.1325¥3,397.5000; 10000¥0.4715¥4,715.0000

Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
±24 mA output drive (V_CC = 3.0 V)
CMOS low power dissipation
I_OFF circuitry provides partial Power-down mode operation
Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8-B/JESD36 (2.7 V to 3.6 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Overvoltage tolerant inputs to 5.5 V
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C