74AUP1G38GX,125

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74AUP1G38

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商品编号:
74AUP1G38GX,125
简述:
Low-power 2-input NAND gate (open drain)
描述:
The 74AUP1G38 is a single 2-input NAND gate with open-drain output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
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库存：10,000

价格（包含13%的增值税）

数量单价总价: 1¥0.4919¥0.4919; 500¥0.4472¥223.6000; 1000¥0.4259¥425.9000; 3000¥0.4056¥1,216.8000; 10000¥0.3588¥3,588.0000

Wide supply voltage range from 0.8 V to 3.6 V
CMOS low power dissipation
High noise immunity
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
Low static power consumption; I_CC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial Power-down mode operation
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C